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Test Number : FN0-202
Test Name : FNC4-7E Foundry Networks Certified Layer 4-7 Engineer
Vendor Name : Foundry
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Foundry 4-7 test

eFPGA IP Density, Portability & Scalability | FN0-202 Latest courses and test Braindumps

by Flex Logix applied sciences, Inc.

There are varied eFPGA suppliers in the market nowadays: Achronix, Adicsys, Efinix, Flex Logix™, Menta, QuickLogic.

There are three diverse enterprise fashions and engineering approaches to eFPGA which be sure you remember to examine how it will have an effect on your success in using their eFPGA IP and their viability as a company long run.

FPGA Chip companies proposing eFPGA IP

FPGA chip businesses often build a new era of FPGAs every ~3 years when there is a major boost in system know-how.

They opt for one foundry, one node, one version of that node and do full-custom circuit design with typically the optimum or near-optimum variety of metallic layers with the intention to get the optimum density FPGA they can. It takes them many of the 3 years to do the complicated engineering required.

on the grounds that FPGA clients want a number sizes and a few variation in the ratio of alternate options like DSP/RAM, the FPGA chip groups will construct their FPGAs from some modular items: a block of LUTs, a DSP block, and typically a block-RAM (twin port). The 3-10 different sizes of the FPGA are put together from the blocks with circuit designers tuning the mesh interconnects and i/O’s for the array measurement.

Their company mannequin is to optimize to make the finest FPGAs. What occurs when they deliver embedded FPGA IP?

1st There are usually dozens of steel stacks that a foundry helps. The bottom four-7 layers, reckoning on the manner, are commonly ordinary because of basis IP like standard cells and reminiscences. Above that, some valued clientele want fewer layers for lessen charge for more straightforward circuits; others want maximum layers for huge, complicated circuits. there are many adaptations of thicknesses/widths with the aid of layer to optimize for each and every customers design. FPGA groups always design their chip with highest or close-optimum steel layers which vastly limits the supported metallic stacks to one or two. If a client needs a different metal stack, they must re-route. If the customer needs the equal number of metal layers however with adaptations in thickness for one of the vital layers, timing will should be redone and likely re-routing of the total design together with circuit changes to offset timing/DRC considerations with thicker/thinner metallic. If the customer wishes fewer metallic layers, it can be unattainable: most likely the FPGA chip makes use of the number of layers it does since it changed into no longer viable to route with fewer layers. The time to do all this work is likely four-6 months with enormous engineering fee.

2nd Foundries constantly increase every of their system nodes for yields, fewer metallic layers and shrinks with a brand new version every year or so. considering FPGA chip groups do full-custom design, they're going to deserve to re-simulate and sure re-design dissimilar parts of their chip to aid the incremental alterations to the technique. (Whereas regular cells are often useable throughout 2 or 3 incremental variations as a result of they use less aggressive common sense design suggestions AND the Copyright 2017, Flex Logix applied sciences, Inc. Flex Logix and EFLX are trademarks of Flex Logix. Achronix, Adicsys, Menta, QuickLogic, Efinix are logos of their respective house owners. foundries are attempting to preserve the commonplace cells the equal for their valued clientele emigrate readily to the more recent manner edition).

3rd assisting various array sizes and alternate options (DSP, RAM) requires custom engineering: the blocks may be modular, but the connections between them and most importantly the interconnect will should be redone exceptionally due to the fact that the quantity of interconnects grows with N2 for mesh interconnect designs. And the I/O ring is customized for every diverse array measurement.

4th considering the GDS changes for each metallic stack and array size and process edition, it is uneconomical to do a validation chip for every GDS exchange.

determine 1: usual 2d-Mesh Interconnect diagram illustrates the non-uniformity of a mesh community across the FPGA. Any change to the area or configuration would require re-imposing the interconnect, comfortably developing a new embedded FPGA implementation.

The FPGA chip groups were in enterprise >10 years however present eFPGA on simplest just a few nodes.

The engineering funding to assist diverse array sizes and alternate options and steel stacks inside an latest node/edition are significant; the engineering investment to port a full-customized design to a new node are a whole lot greater (that’s why FPGA businesses continually only do a era every few years).

this is likely why the big FPGA chip agencies don’t bother with eFPGA: it is a costly distraction to their primary company with, for them, a low return on funding.

Pure eFPGA IP agencies: delicate IP

eFPGA gentle IP companies offer a software device so that it will generate RTL for an array in response to inputs similar to array dimension, I/O count, and so forth. The client can then use EDA tools with a typical mobile library to implement the eFPGA in any method – but the density is terribly low: FPGAs are very regular and benefit from structured placement. This method has some use in examine chips or very low quantity items such as aerospace/protection.

One of those agencies now presents difficult IP on a couple of foundries/nodes. For that business, their optimum array measurement is <<10K and there are only a handful of sizes/choice combinations to choose from. Density for the smallest arrays is ~0.5x of a full-custom FPGA; and for the biggest arrays ~1/3 of a full-custom FPGA. presumably what's happening is the N2 complexity growth in interconnect for larger arrays. Their greatest array is 2x the LUTs and Flip-Flops of their midsize array, but is ~3x the silicon area! This fashion in interconnect complexity growth is doubtless why there aren't any big arrays provided. The variety of metal layers required or the latitude of metal stacks they are appropriate with isn't public.

every array dimension is a special design so a validation chip for one does not prove the others. Doing a validation chip for each array size is uneconomical.

Pure eFPGA tough IP: Flex Logix

Flex Logix is the youngest of the companies featuring eFPGA however offers eFPGA on greater system nodes/variations (7 foundry and 1 captive) and over a much wider range of sizes than any competitor.

We began the business in response to Cheng Wang’s revolutionary interconnect which he developed working with others at UCLA whereas doing 5 diverse FPGA check chips of expanding complexity over assorted manner nodes previous to beginning Flex Logix.

In ordinary FPGAs, the FPGA fabric is 70-80% interconnect and best 20-30% of the area is common sense/LUTs.

Cheng’s check chips were restrained in dimension by way of budget suppliers: To get greater good judgment on the chip he came up with a brand new interconnect that become an awful lot denser than the ordinary mesh. And its’ complexity grows more slowly than mesh for better array sizes.

figure 2: Illustration of Flex Logix interconnect leading to a plenty extra efficient interconnect in comparison to a traditional interconnect.

Cheng’s interconnect as developed at UCLA became the field of a paper that gained the fantastic Paper Award at ISSCC in 2014 and of a patent currently issued to UCLA, of which Flex Logix is the exclusive licensee. for the reason that beginning Flex Logix, Cheng has made numerous advancements to the interconnect, a few of which resulted in two recently issued patents.

The culmination is that Flex Logix can use typical cells for swift implementation and portability across incremental procedure variations, while achieving density pretty much the equal as eFPGA from full-customized FPGA chips: the increased density of the interconnect offsets the lesser density of the common cells. The positive density of EFLX eFPGA is further accelerated by using the better utilization they obtain compared to normal FPGA interconnect.

In 40nm their IP is suitable with two diversifications; in 28nm their IP is appropriate with two adaptations; and in 16nm their IP is appropriate with three adaptations.

further, Flex Logix’ interconnect does not want maximum metallic layers: in 40nm, 28nm and 16nm their eFPGA IP is suitable with just about all steel stacks.

Array size Scalability

after they all started Flex Logix, they realized in early talks with potential consumers that purchasers desired both silicon confirmed and a wide array of array sizes. They realized that designing say 10 distinctive array sizes would mean needing to have 10 distinctive validation chips: this wasn’t feasible and not validating in silicon would imply unacceptable possibility for the client.

So Cheng came up with an imaginitive solution: make an eFPGA IP core which is an entire FPGA by itself which can also be tiled, without GDS adjustments, to make a extremely wide range of array sizes.

for instance, the EFLX®4K IP core is an entire embedded FPGA of 4K LUT4s with >600 inputs and >600 outputs. however the EFLX4K also has a correct-layer interconnect, no longer proven within the block diagram to the right, which immediately extends between cores when abutted enabling ~50 array sizes up to 200K LUTs. Any array configuration vital for a chip may also be generated within just a few days: many of the time is generating the .LIB data throughout a large number of technique corners, considering the fact that timing is achieved at the array level.

figure three: Diagram of an EFLX Array. through arraying a validated embedded FPGA core, arrays of diverse sizes are validated with the aid of design as a result removing hazards linked to new embedded FPGA implementations on a given process.

we now have an EFLX150 core for smaller array requirements; and at some point they are able to enforce an EFLX16K core when purchasers need up to 800K (or bigger) LUT4 arrays.

Plus they now have two types of each IP core: all common sense and good judgment with ~20% of the area replaced by using Multiplier-Accumulators: both types are the exact same dimensions so that they will also be intermixed to provide consumers the ratio of DSP-to-logic they need.

Silicon proven IP to your Node/version, Your steel Stack and Your Array dimension

When Flex Logix ports an EFLX IP core to a brand new system, it builds a validation chip with as a minimum a 2x2 array (this verifies that the desirable degree interconnect extension works on all 4 sides) on a die with PLLs, PVTs and connected SRAM so trying out can be performed at high speeds (>1GHz on 16nm), at real voltages and severe temperatures to validate silicon function and efficiency. they now have built 4 validation chips to date in 40nm, 28nm and 16nm (two: one for the EFLX150 and one for EFLX4K).

on account that an EFLX array is built by using abutting EFLX cores with out a GDS changes, the EFLX Array you get is universal decent for your size and your node/model.

we now have confirmed this by using fabricating a 7x7 array of EFLX4K cores (EFLX200K = 200K LUT4s) in 16nm which is in validation now. it's totally useful, changed into Verified at ARM TechCon running their Flex Micro architecture. Now efficiency measurements are being achieved over temperature and voltage.

Conclusion

Flex Logix offers you the maximum density, most flexibility on technique adaptations/metallic stacks, and widest latitude of array sizes whereas ensuring the GDS you utilize has been confirmed in silicon.

we're happy to go into greater aspect on any of the above analysis.

if you wish to get a replica of this white paper, click on right here


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