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000-957 exam Dumps Source : IBM XIV Storage System Technical(R) Solutions V3

Test Code : 000-957
Test title : IBM XIV Storage System Technical(R) Solutions V3
Vendor title : IBM
: 195 actual Questions

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IBM IBM XIV Storage System

IBM Brings SSD Caching aid to the XIV Gen3 Storage device | killexams.com actual Questions and Pass4sure dumps

IBM has lately announced that it has brought a collection of latest enhancements to its XIV Storage system Gen3, including sheperd for a brand novel solid condition power (SSD) caching choice, that is declared to boost device efficiency by as much as thrice.

based on IBM, going for the IBM XIV SSD Caching altenative provides up to 6TB of fast-examine SSD storage to its techniques, which is positioned between the materiel memory and tough drives.

here's then used as a mercurial cache for the most often accessed records, as a result dramatically reducing latency times when in comparison to mechanical storage.

"These newest updates to XIV Gen3 are a pretty Good illustration of IBM's persevered commitment to helping customers obtain industry effects via smarter storage technologies," spoke of Doug Balog, vice chairman and company line executive for IBM Storage systems.

"It comes entire the way down to saving consumers time and money with extremely efficient, with ease managed, virtualized, and high-performing storage programs enjoy XIV Gen3," concluded the enterprise’s rep.

in addition to IBM XIV SSD Caching, IBM announced the skill to reflect statistics between previous versions of XIV and XIV Gen3 methods, on the way to ease statistics migration and assist give valued clientele flexibility to repurpose their XIV models as catastrophe healing backup techniques.

The XIV Storage device Gen3 was delivered by IBM in the seat of ultimate year as a novel era of storage options designed to lessen the total can suffuse of possession, and improve device efficiency by means of four instances over the fragile model.

With XIV Gen3, IBM additionally changed the system's Ethernet-based mostly backplane with a high-efficiency InfiniBand backplane, that accelerated the device's inner bandwidth between modules by way of forty times.

The XIV Storage system Gen3, in conjunction with its SSD Caching alternative, is purchasable birthright now from IBM, with pricing being supplied upon request.

IBM SONAS positive factors coverage-pushed tiering, gateway to IBM XIV Storage device | killexams.com actual Questions and Pass4sure dumps

IBM is bettering its Scale Out community connected Storage (IBM SONAS) system first launched in February, including policy-pushed file tiering, bigger skill drives and a gateway that integrates the NAS with the IBM XIV obstruct storage device.

furthermore, IBM has moved to the midrange with its virtual tape library (VTL) facts deduplication platform, launching the materiel Storage TS7610 ProtecTier Deduplication appliance categorical.

IBM previewed the tiering capabilities when it first announced the SONAS system, which is in line with IBM's customary Parallel File materiel (GPFS). They let purchasers accelerate records across storage tiers on disk and tape promptly in response to guidelines. here's enabled by using the SONAS coverage engine that IBM claims can scan 10 million data per minute per node and straight away scan billions of files when the nodes are utilized in parallel.

The XIV gateway lets SONAS purchasers spend XIV disk for returned-conclusion storage, bringing SONAS scanning and tiering capabilities to the XIV Storage equipment.

all through IBM's earnings title Monday nighttime, the supplier's executives spoke of the XIV Storage system delivered greater than one hundred thirty consumers ultimate quarter and revenue more than doubled from final 12 months. IBM storage advertising manager Brad Johns mentioned he anticipates purchasers the spend of IBM SONAS with XIV Storage device to deliver obstruct and file storage together. "we will give well-nigh unified storage based on XIV," he stated. "The equal XIV may well be providing obstruct statistics to a collection of transactions and built-in to SONAS for file storage."

SONAS additionally now supports 600 GB SAS drives – up from 450 GB – and asynchronous replication between two methods at any distance for cataclysm restoration.

Mike Kahn, an analyst at the Clipper neighborhood Inc., observed he considers it a positive that IBM is integrating the methods rather than selling entire of its storage as isolated structures.

"IBM has a vast richness of items, however there is a criticism that they haven't been tying these products to each and every different," Kahn observed. "So here's a positive component as far as i'm involved. I mediate it's more for XIV shoppers who're in location, no longer to sell XIV in the back of the SONAS."

SONAS offers IBM two NAS systems – it additionally sells NetApp's FAS storage programs beneath the IBM N collection company. IBM's Johns famed the N collection is the company's platform for mainstream NAS, while SONAS is aimed at consumers "dealing with very big portions of information. certainly, excessive-performance computing is one of those markets. They view this as complementing their N series. In environments where managing numerous N sequence programs is attending to be burdensome, this is the site this would healthy."

The Clipper community's Kahn famed the line between both products remains clear. "SONAS is a huge-scale answer," he observed. "if you're looking at anything of a modest dimension, their version of the NetApp product line is acceptable."

ProtecTier scales down, takes on EMC data area

The TS7610 ProtecTier Deduplication appliance categorical product is the first midrange virtual tape library IBM has delivered due to the fact it entire started delivery the dedupe VTL platform in 2008 after acquiring Diligent technologies Inc.

IBM's Johns talked about IBM has offered 800 licenses for the TS7650 ProtecTier commercial enterprise platform. The TS7610 is smaller (as much as four.5 TB of usable skill in 3U) and less expensive (beginning at $50,000) than the TS7650 and springs packaged with servers, adapters and storage. The TS7610 makes spend of SAS disk, while the TS7650 clients Fibre Channel drives. each delight in virtual tape library interfaces, however Johns referred to IBM is in view that types with Ethernet connectivity.

IBM referred to the smaller programs delight in a sustained throughput of 80 MBps, and up to 12 TS7610s can replicate to a TS7650 in a vital location.

Johns talked about the leading competitors for the TS7610 is EMC Corp.'s statistics domain DD6000 platform.

IBM speeds up XIV Storage gadget Gen3 With SSD Caching | killexams.com actual Questions and Pass4sure dumps

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IBM XIV Storage System Technical(R) Solutions V3

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Front Panel build and features of Dell Power edge R730 | killexams.com actual questions and Pass4sure dumps

Dell Power Edge R730

The power Edge R730 is a two-socket 2U rack server with impressive processor performance, a big memory footprint, extensive I/O options.

The R730 supports up to two Intel Xeon E5–2600 v3 processors, up to 24 DIMMs, and 16 arduous drives or SSDs.

The R730 has the traditional rack-mount server design with a heavy, robust and extremely well engineered all-metal chassis design with a lift-off lid for ease to service.

Dell Power Edge R 730 front panel

Font Panel:

The R730 supports up to 16 x 2.5” or up to 8 x 3.5” front-accessible, hot-plug arduous drives that are secured by a removable front bezel.

Other front-panel features comprise an interactive LCD control panel, USB management port/iDRAC Direct, a video connector and a vFlash media card slot.

Power-on indicator, power button: The power-on indicator lights when the system power is on. The power button controls the power supply output to the system.

NMI button :Used to troubleshoot software and device driver errors when running inevitable operating systems. This button can be pressed using the quit of a paper clip. spend this button only if directed to conclude so by qualified back personnel or by the operating system documentation.

LCD menu buttons: Navigate the control panel LCD menu

System identification button: The identification buttons on the front and back panels can be used to locate a particular system within a rack. When one of these buttons is pressed, the system status indicator on the back flashes until one of the buttons is pressed again. Press to toggle the system ID on and off.

Video connector :Connect a VGA display to the system.

Information tag: A slide-out label panel which allows to record system information such as Service Tag, NIC, MAC address .

USB management port/ iDRAC Direct:Connect USB devices to the system or provides access to the iDRAC Direct feature

Hard drives: Up to eight 3.5 inch hot-swappable drives

USB connector: Connect USB devices to the system. The ports are USB 2.0-compliant.

Quick Sync (optional) :Indicates a Quick Sync enabled system. The Quick Sync feature is optional and requires a Quick Sync bezel. This feature allows management of the system using mobile devices. This feature aggregates hardware/firmware inventory and various system even diagnostic/error information that can be used in troubleshooting the system

Optical drive (optional): One optional SATA DVD-ROM drive or DVD+/-RW drive

vFlash media card slot :To insert a vFlash media card.

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When Databases Meet FPGA: Achieving 1 Million TPS With X-DB Heterogeneous Computing | killexams.com actual questions and Pass4sure dumps

X-Engine is a novel generation storage engine developed by Alibaba Database Department and is the basis of the distributed database X-DB. To achieve 10 times the performance of MySQL and 1/10 the storage cost, X-DB combines software with hardware to develop complete spend of the most cutting-edge technical advantages in both software and hardware fields.

FPGA acceleration is their first attempt in the custom computing field. At present, the FPGA-accelerated X-DB has been subject to small-scale online grayscale release. FPGA will assist X-DB in the 6.18 and Double 11 shopping carnivals this year and will meet Alibaba's industry departments' tall database performance requirements.

Overview of Alibaba's X-Engine

Owning the world's largest online transaction website, Alibaba's OLTP (online transaction processing) database system needs to answer high-throughput service requirements. According to their statistics, several billion records win written into their OLTP database system on a daily basis. During the 2017 Double 11 (Singles' Day) shopping carnival, the system's peak throughput reached 10 million TPS (transactions per second). Alibaba's industry database systems mainly delight in the following characteristics:

  • High transaction throughput and low latency in write and read operations.
  • Write operations develop up a relatively tall harmony in comparison to that of traditional databases; the read to write workload ratio usually is more than 10:1. However, the number for Alibaba's transaction system reached 3:1 on the day of the 2017 Double 11 shopping carnival.
  • Data access hotspots are relatively concentrated. A newly written data record will be accessed mainly (99%) within the first seven days, and the possibility it may be accessed later is extremely low.
  • To meet Alibaba's stringent requirements on performance and cost, they delight in designed a novel storage engine; it is called X-Engine. They delight in used many cutting edge database technologies in X-Engine; these comprise highly-efficient memory index structures, asynchronous write assembly-line processing mechanism, and optimistic concurrency control for in-memory databases.

    To achieve the best write performance and facilitate the separation of artic and peppery data for tiered storage, X-Engine has borrowed the design of LSM-Tree. X-Engine maintains multiple memtables in its memory. It appends entire newly written data to these memtables, rather than directly replacing existing records. As the data storage is relatively large, it is impossible to store entire data in memory.

    When data in memory reaches a specified volume, they flush it to the persistent storage to configuration an SSTable. To reduce latency in read operations, X-Engine regularly schedules compaction tasks to compact SSTables in the persistent storage. X-Engine merges key-value pairs in multiple SSTables by keeping only the latest version of key-value pairs if multiple versions exist (all key-value pair versions currently referenced by transactions will besides be kept).

    Based on the characteristics of data access, X-Engine applies tiered storage to persistent data, where they store energetic data in relatively tall data layers, and merge less energetic data (seldom accessed) with base-layer data and store it in the base-layer. It compresses base-layer data at a tall compression rate and migrates it to storage media featuring big capacity but the relatively low price (such as SATA HDDs) to achieve the goal of storing a big quantity of data at a relatively low cost.

    In this case, tiered storage creates a novel problem: the system must frequently compact data, and the larger number of data writes requires more frequent compaction processes. Compaction is a compare and merge process which requires tall consumption of CPU and storage I/O. In high-throughput write cases, a big number of compaction operations will occupy a big number of system resources. This can surely judgement the performance of the entire system to drop tremendously thus leading to a huge repercussion on the application system.

    The completely novel X-Engine has extraordinary multi-core expansion capability to achieve very tall performance. Its front-end transaction alone can almost completely consume entire CPU resources, and it has a much higher resource using efficiency than InnoDB. They delight in shown the comparison between the two in the following figure:

    Image title

    At such a performance level, the system does not delight in any other resources for compaction operations; otherwise, performance levels will drop.

    Based on their testing results, in DbBench benchmark's write-only scenario, the system periodically suffers from performance jitter. When a compaction task occurs, the system performance drops by more than 40%, and when the compaction task ends, the system performance returns to normal. They delight in shown this conduct in the following figure:

    Image title

    However, if they conclude not conduct compaction promptly, the accumulation of multi-version data can seriously affect the read operations.

    To solve the performance jitter caused by compaction, academic experts delight in build forward many structures such as VT-tree, bLSM, PE, PCP, and dCompaction. Although these algorithms can optimize the compaction performance across multiple aspects, they cannot reduce consumption of CPU resources by compaction. Based on material research statistics, when using SSD storage devices, the computing operations of compaction in the system consumes approximately 60% of computing resources. Therefore, no matter what optimizations they implement for compaction in the software layer, for entire LSM tree-based storage engines, performance jitter caused by compaction is always an Achilles' heel.

    Fortunately, special hardware opens a novel door for solving performance jitter caused by compaction. In fact, it has become a trend to spend special hardware in solving traditional databases' performance bottlenecks. They delight in already offloaded database operations such as Select and Where to FPGA, and more knotty operations such as Group By are under research. However, the current FPGA acceleration solutions delight in a brace of drawbacks:

  • The current acceleration solutions are designed for the SQL layer; FPGA is generally placed between storage and host and is used as a filter. Although, researchers delight in made numerous attempts to spend FPGA to accelerate the OLAP system, the FPGA acceleration design for the OLAP system remains a challenge.
  • While FPGA's chip size is getting smaller and smaller, FPGA's internal errors such as unique event upset (SEU) pose greater and greater threats to FPGA reliability. For a unique chip, the probability of internal error is 3-5 years. Therefore, the fault tolerance mechanism design becomes vitally necessary for systems in necessity of large-scale availability.
  • To ease the repercussion of compaction on X-Engine's system performance, they delight in used an asynchronous hardware device FPGA, rather than the CPU to complete the compaction operation. This approach is crucial for a storage engine that satisfies stringent service requirements by maintaining the overall system performance at a high-level and avoiding performance jitters. Here are the major design features:

  • Highly efficient design and implementation of FPGA compaction: Using streamlined compaction operations, FPGA compaction achieves a processing performance 10 times the CPU single-thread processing performance
  • Hybrid storage engine's asynchronous scheduling logic design: As FPGA can complete compaction's link requests in milliseconds, using a traditional synchronous scheduling system will obstruct a big number of compaction threads and judgement massive thread-switching cost. Through asynchronous scheduling, they delight in successfully reduced the thread-switching cost and improved the system's engineering availability.
  • Fault tolerance mechanism design: As limits of entered data and FPGA internal errors may judgement a rollback of some compaction tasks, to ensure data integrity, entire tasks that delight in been rolled back by FPGA will be re-executed by the equivalent CPU compaction threads. The fault tolerance mechanism design as described in this article meets Alibaba's actual industry requirements and avoids FPGA's internal instability.
  • X-Engine Compaction

    X-Engine's storage structure contains one or multiple memory buffer areas (memtable), and multilayer persistent storage L0, L1... Each layer contains multiple SSTables.

    Image title

    When memtable is full, it turns into an immutable memtable and then flushes to an SSTable to L0. Each SSTable contains multiple data blocks and one index obstruct to index the data block. When it reaches the maximum number of L0 files, it triggers the merge of SSTables that delight in the overlapped key ranges; this process is called compaction. Likewise, when they achieve the maximum number of SSTables at a layer, it merges with lower layer data. In this way, artic data constantly flows downward while peppery data remains at a relatively higher layer.

    We can specify a orbit of key-value pairs that merge during a compaction process and this orbit may accommodate multiple data blocks. Generally, a compaction process involves merging data blocks between two adjacent layers. However, they necessity to pay special attention to compaction tasks between L0 and L1. This is because as SSTables in L0 directly flushes from the memory, keys of SSTables in this layer may win overlapped. Therefore, a compaction task between L0 and L1 may involve merging multiple data blocks.

    Image title

    For read operations, X-Engine needs to search for the required data from entire memtables. If it fails to find the data in memtables, it searches in the persistence storage, from higher to lower layers. As a result, timely compaction operations not only abbreviate the read path but besides reclaim the storage space. However, this system uses a lot of system computing resources and causes performance jitter. This is an pressing problem that X-Engine must solve.

    FPGA Accelerated Database

    From the perspective of the existing FPGA accelerated databases' status quo, they can divide FPGA accelerated database architectures into two types; the bump-in-the-wire design and the hybrid design. In the early stage, because of the FPGA card's insufficient memory resources, the former sort of architecture is relatively popular. In this architecture, they site FPGA on the storage data path and spend the host as a filter. The odds is that it requires zero data replication, while the drawback is that the acceleration operation must be a fragment of the streamlined process, therefore making it not supple enough in terms of the design method.

    The latter architecture design uses FPGA as a coprocessor, where they delight in connected FPGA to host via PCIe and spend the DMA system for data transmission. As long as the offloading computation is intensive enough, data transmission costs are acceptable. The hybrid architecture design allows more supple offloading methods. For knotty operations such as compaction, data transmission between FPGA and host is necessary. Therefore, they delight in used the hybrid architecture design for hardware acceleration in their X-Engine.

    Image title

    System Design

    In traditional LSM-tree-based storage engines, CPU is liable for handling balanced user requests, as well as the scheduling and execution of compaction tasks. In other words, CPU is both the producer and consumer of compaction tasks. However, in a CPU-FPGA hybrid storage engine, CPU is only liable for producing and scheduling compaction tasks. In this method, they necessity to offload the execution of compaction tasks to the special hardware (FPGA).

    Image title

    For X-Engine, handling of balanced user requests is similar to that of LSM-tree-based storage engines:

  • A user submits a request to operate on a specified KV pair (Get/Insert/Update/Delete). In the case of a write operation, a novel record appends to a memtable.
  • When a memtable reaches its maximum size, it turns into an immutable memtable.
  • The immutable memtable then turns into an SSTable and flushes to the persistent storage.
  • When L0 reaches the maximum number of SSTables, compaction gets triggered. They can divide offloading of a compaction task into the following steps:

  • CPU splits Load SSTables (that necessity to be compacted from the persistent storage) into multiple compaction tasks at the granularity of data blocks following the metadata, and pre-allocates memory space for computation result of each compaction task. Consequently, it pushes each successfully created compaction task into the task Queue for FPGA to execute.
  • CPU reads the status of Compaction Units on FPGA and allocates compaction tasks from the task Queue to available Compaction Units.
  • It transmits Input data to FPGA's DDR via DMA.
  • A Compaction Unit executes the compaction task and transmits the computation result via DMA back to the host; it attaches a recur code to testify the status of this compaction task (fail or success). Next, it pushes the compaction results of finished tasks to the Finished Queue.
  • The CPU checks the compaction result status in the Finished Queue. If a compaction task fails, the CPU executes it again.
  • It flushes the compaction results to storage.
  • Detailed Design FPGA-Based Compaction

    Compaction Units (CU) are the basic unit for FPGA to execute compaction tasks. An FPGA card can site multiple CUs, and each CU is composed of the following modules:

    Image title

    1. Decoder: In X-Engine, they store a KV in the data obstruct after compression and encoding. The primary office of the Decoder module is to decode KV pairs. Each CU contains 4 Decoders, and a CU back a compression task of a maximum of 4 KV pairs. They necessity to split the compression tasks that require compression of more than 4 KV by the CPU. Based on their assessment, most compression tasks involve less than 4 KV pairs. They delight in placed 4 Decoders based on their considerations of performance and hardware resources. Comparing the configuration with 2 Decoders, we've increased 100% hardware consumption but obtained 300% performance improvement.

  • KV Ring Buffer: KV pairs decoded by the Decoder module win temporarily stored in KV Ring Buffer. Each KV Ring Buffer maintains a read indicator (maintained by the Controller module) and a write indicator (maintained by the Decoder module). KV Ring Buffer maintains three signals to testify the current status: FLAG_EMPTY, FLAG_HALF_FULL, and FLAG_FULL. If FLAG_HALF_FULL is at a low level, the Decoder module will continue decoding KV pairs. Conversely, the Decoder module will quit decoding KV pairs until downstream consumers in the pipeline delight in consumed the decoded KV pairs.
  • KV Transfer: This module is liable for transmitting keys to Key Buffer. Because merging KV pairs only involve comparison of key values, the values conclude not necessity to be transmitted. They can track the currently compared KV pairs by using the read indicator.
  • Key Buffer: This module stores keys of each KV pair that necessity to be compared. When entire keys that necessity to be compared delight in been transmitted to the Key Buffer, the Controller notifies the Compaction PE to compare them.
  • Compaction PE: The Compaction Processing Engine (compaction PE) is liable for comparing key values in Key Buffer. Comparison results are sent to the Controller, and then the Controller sends a notice to KV Transfer to transmit the corresponding KV pair to the Encoding KV Ring Buffer for the Encoder module to encode them.
  • Encoder: The Encoder module is liable for encoding KV pairs from the Encoding KV Ring Buffer into a data block. If the data obstruct reaches its maximum size, then the current data obstruct gets flushed to DDR.
  • Controller: The Controller acts as a coordinator in CU. Although the Controller is not a fragment of the compaction pipeline, it plays a key role in each step of the compaction pipeline design.
  • A compaction process contains three key steps: decoding, merging, and encoding. The most significant challenge for designing a proper compaction pipeline is that the execution time for each step varies significantly. For example, because of parallel processing, the throughput of the decoder module is much higher than the encoder module. Therefore, they must suspend some mercurial modules to wait for downstream modules silent in the pipeline. To match the throughput differences in each of the pipeline's modules, they delight in designed a Controller module to coordinate different steps in the pipeline. An additional capitalize of this design is that it decouples each module in the pipeline and enables more supple development and maintenance during engineering implementation.

    Image title

    When integrating FPGA compaction into X-Engine they hope to delight in independent CU throughput performance; the baseline of the experiment is the CPU.

    Single-core compaction thread (Intel(R) Xeon(R) E5-2682 v4 CPU with 2.5 GHz)

    Image title

    We can draw the following three conclusions from the experiment:

  • n entire KV lengths, FPGA compaction has a higher throughput than that of a single-thread CPU; this proves the feasibility of compaction offload;
  • With the augment of KV lengths, FPGA compaction throughput reduces. This is because the lengths of bytes that necessity to be compared delight in increased, resulting in the augment of cost for comparison.
  • The acceleration rate (FPGA throughput / CPU throughput) increases with the value length. This is because when the KV length is short, it requires frequent communication and status checking among different modules; this means a relatively tall cost in comparison with balanced pipeline operations.
  • Asynchronous Scheduling Logic Design

    Because a link request in FPGA is completed in milliseconds, using the traditional synchronous scheduling system will judgement tall thread switching costs. Based on FPGA's characteristics, they delight in redesigned an asynchronous scheduling compaction method, where:

  • The CPU is liable for structure compaction tasks and pushing them into the task Queue.
  • A thread pool is maintained to deal compaction tasks to specified CUs.
  • When a compaction task is finished, it will be pushed to the Finished Queue.
  • The CPU will then check the task execution status, and schedule CPU compaction threads to re-execute the failed compaction tasks.
  • Asynchronous scheduling significantly reduces the thread-switching cost of CPU.

    Image title

    Fault Tolerance Mechanism Design

    For FPGA compaction, the following three reasons can lead to the failure of compaction task:

  • Data gets damaged during the transmission process: calculate the CRC values of data before and after transmission, and compare the values. If these two CRC values are inconsistent, it means that the data is damaged.
  • FPGA internal errors (bit upset): To solve this problem, they delight in attached an additional CU to each CU. They can compare the computation results of both CUs and any inconsistency in the results will testify that a bit upset error has occurred.
  • Input data of a compaction task is invalid: To facilitate FPGA compaction design, they delight in set a restriction on the length of KVs. The compaction tasks for KVs that exceed the maximum allowable length are identified as invalid tasks.
  • To ensure the data is correct, the CPU will conduct computation again on entire failed tasks. As they mentioned earlier in the fault tolerance mechanism, they delight in addressed a wee fragment of compaction tasks that exceed the limits and delight in avoided the risk of FPGA internal errors.

    Image title

    Experiment Results Lab environment
  • CPU: 64-core Intel (E5-2682 v4, 2.50 GHz) processor
  • Memory: 128 GB
  • FPGA card: Xilinix VU9P
  • memtable: 40 GB
  • block cache 40 GB
  • We compared the performance of two storage engines:

  • X-Engine-CPU: compaction operation executed by CPU
  • X-Engine-FPGA: compaction offloaded to FPGA for execution
  • DbBench

    Image title

    Result analysis:

  • n a write-only scenario, X-Engine-FPGA sees a 40% throughput increase. From the performance curve they can expose that when compaction begins, the performance of X-Engine-CPU drops by 1/3.
  • FPGA compaction has a higher throughput and is faster, so the read path is shortened faster. Therefore, in the read/write hybrid scenario, X-Engine-FPGA throughput increases by 50%.
  • The throughput in the read/write hybrid scenario is smaller than that of the write-only scenario. Read operations require access to data stored in persistent layers which brings in I/O cost and affects the overall throughput performance.
  • These two performance curves limn two different compaction statuses. In the left figure, the system performance jitters periodically meaning that the compaction operation is competing with balanced transaction handling threads for CPU resources; while in the birthright figure, X-Engine-CPU's performance maintains at a low-level meaning that the compaction hasten is smaller than the write speed, causing accumulation of SSTables. Compaction tasks are subject to constant scheduling at the backend.
  • CPU schedules the Compaction tasks. That's why X-Engine-FPGA's performance besides jitters and the curve is not smooth.
  • YCSB

    Image title

    Result analysis:

  • On YCSB benchmark, due to the influence of compaction, X-Engine-CPU's performance decreases by approximately 80%. However, for X-Engine-FPGA, its performance only sees a fluctuation of 20% due to the influence of the compaction scheduling logic.
  • The check-unique logic introduces read operations. With the augment in pressure testing time, the read path becomes longer, and the performance of both storage engines decreases with time.
  • In the write-only scenario, X-Engine-FPGA's throughput increases by 40%. However, with the augment in the read/write ratio, the acceleration result of FPGA Compaction decreases gradually. When the read/write ratio becomes higher, the write pressure becomes smaller, and the SSTable accumulation becomes slower thus reducing the number of threads that handle compaction tasks. Therefore, X-Engine-FPGA sees a more obvious performance augment in write-intensive workloads.
  • With the augment in the read/write ratio, the throughput increases. When write throughput is smaller than that of the KV interface, the cache miss ratio is relatively low, thus avoiding frequent I/O operations. With the augment in the harmony of write operations, the number of threads that handle compaction tasks besides increases, thus reducing the system's throughput capability.
  • Image title

    Result analysis:

  • With FPGA acceleration, X-Engine-FPGA's performance improves by 10%–15% when the number of connections is increased from 128 to 1024. When the number of connections increases, the throughput of both systems gradually decreases because of the lock competition of hotspot rows increases.
  • TPC-C's read/write ratio is 1.8 : 1. In the experiment, under the TPC-C benchmark, more than 80% of CPU resources were consumed on SQL resolution and lock competition of hotspot rows. The actual write pressure was not very heavy. Based on their observation in the experiment, the number of threads that execute compaction tasks in the X-Engine-CPU is no more than three (a total of 64 cores). Therefore, FPGA's acceleration result is not as obvious as the previous instances.
  • SysBench

    We delight in included testing for InnoDB in this experiment (buffer size = 80 GB)

    Image title

    Result analysis:

  • X-Engine-FPGA improves more than 40% of throughput performance. Because SQL resolution consumes a big number of CPU resources, the throughput of DBMS is smaller than that of the KV interface.
  • X-Engine-CPU reaches a poise at a low level. Because the compaction hasten is slower than the writing speed, SST files are accumulated, and compaction is constantly scheduled.
  • X-Engine-CPU's performance is twice that of InnoDB, which shows the odds of LSM tree-based storage engines in a write-intensive scenario;
  • In comparison with the TPC-C benchmark, Sysbench is more similar to Alibaba's actual transaction scenario. For a transaction system, most queries are data insertion queries and simple point queries and seldom involve orbit queries. A subside in hotspot row conflicts causes the number of resources consumed in the SQL layer to decrease. During the experiment, they delight in observed that for X-Engine-CPU, when more than 15 threads are used to execute compaction tasks, the performance improvement brought by FPGA acceleration is very obvious.
  • Conclusion

    In this article, the X-Engine storage engine accelerated by FPGA brings 50% performance improvement for the KV interface, and 40% performance improvement for the SQL interface. With the subside in the read/write ratio, FPGA's acceleration result becomes more obvious, thus meaning that FPGA compaction acceleration is suitable for write-intensive workloads. This is consistent with the intention of the LSM-tree design. Also, they delight in avoided FPGA's internal defects by designing a fault tolerance mechanism, and we've finally created a high-availability CPU-FPGA hybrid storage engine that meets Alibaba's actual service requirements.

    It is the first actual project that uses a heterogeneous computing device introduced by X-DB to accelerate core database functions. Based on their experiences, FPGA can completely meet the computing demands raised by X-Engine's compaction tasks. At the selfsame time, they delight in been researching to schedule more suitable computing tasks to FPGA for execution, such as compression, BloomFilter generation, and SQL unite operators. At present, the R&D for the compression office is completed, and it will be built into a set of IP together with Compaction to execute data compaction and compression operations simultaneously.

    X-DB FPGA-Compaction hardware acceleration is an R&D project completed by three parties; these parties are respectively the Alibaba Database Department database kernel team, the Alibaba Server R&D Department custom computing team, and Zhejiang University. Xilinx's technical team has besides made much contributions to the success of this project. They hereby extend their gratitude to them. They will post X-DB online for public beta this year. You will then be able to sustain the significant performance improvement with FPGA acceleration to X-DB.

    Penguin Open Compute Tundra Platform now Available with Haswell V3 | killexams.com actual questions and Pass4sure dumps

    Tundra-OpenHPCToday Penguin Computing announced immediate availability of the Penguin Tundra cluster platform powered by the novel Intel Xeon processor E5-2600 v3 product family. First unveiled at SC13 and based on Open Compute Project rack even infrastructure, Penguin Tundra delivers the highest density and lowest total cost of ownership for tall Performance Technical Computing clusters.

    As the first Penguin-original system design Penguin Tundra is an embodiment of Penguin’s system integration and data seat expertise,” said Tom Coull, CEO and President of Penguin Computing. “Tundra provides density and TCO advantages for current large-scale HPC deployments while designed to accommodate future exascale HPC components such as coprocessors and fabrics.”

    Penguin Tundra delivers a very tall number of dual socket (2P) Intel Xeon E5-2600 v3 compute nodes per rack by combining the Open Rack infrastructure defined by the Open Compute Project with a Penguin original compute node design. Open Rack design utilizes the available physical space more efficiently and features besides a shared, rack level, redundant AC/DC power conversion and distribution.

    We are excited to perceive Penguin Computing offering state-of-the-art HPC solutions powered by the novel Intel Xeon E5-2600 v3 processors,” said Eoin McConnell, Xeon E5 family product line director, Data seat Group. “The enhanced floating point compute performance provided by the novel processors combined with the physical density and efficiency of the Penguin Tundra platform provides a powerful solution for TOP500 supercomputers and commercial HPC clusters.”

    In this video from SC13, Phil Pokorny from Penguin Computing describes the company’s latest open compting innovations for HPC.

    Penguin Computing is focused on testing, integrating and supporting Linux-based compute, storage and networking in the HPC clusters and Internet datacenters. The Penguin Tundra cluster solutions featuring Intel Xeon E5-2600 v3 processors, Penguin IceBreaker storage and Penguin Arctica switches are available immediately worldwide.

    Sign up for their insideHPC Newsletter.

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